3 Dimensional transmission line matrix (3D TLM) modeling and analysis of through silicon via (TSV) coupling in 3 dimensional integrated circuit (3D IC)3차원 전송선 매트릭스 방법을 이용한 3차원 집적회로에서 사용되는 실리콘 관통 비아의 잡음전달 현상에 대한 모델링 및 분석

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3D IC is an IC which is stacked in z-direction. To achieve this stacked system, we need some interconnection method between up and down chips. Wire bonding is the conventional methods, but new technology using Through Silicon Via (TSV) have emerged. TSV has short interconnection length, no limitation of location, and can make small size, so TSV is replacing the role of wire-bonding. However TSV also has some disadvantage like thermal problem, noise coupling problem, and manufacturing issues. In my research, I have focused on the noise coupling issues of TSV. TSV is constructed of conductor via surrounded by insulation layer. Insulation layer is for isolation between silicon substrate and conductor via, but this insulation layer is very thin, have high capacitance. So, for high frequency signal, this insulation layer can``t do its original role, isolation. So this high frequency signal can easily be coupled to active circuit which is located near TSV. And degrade circuit performance. In this paper, I have modeled the coupling path between active circuit and TSV, and analyzed the coupling mechanism of this coupling path, also verified the proposed model by measurement. Then, as an application, proposed and verified noise coupling model was used to PLL for performance degradation simulation
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
419216/325007  / 020083511
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ vi, 66 p. ]

Keywords

coupling; 3D TLM; TSV; 3D IC; 3차원 집적회로; 잡음전달; 3차원 전송선 매트릭스; 실리콘 관통 비아

URI
http://hdl.handle.net/10203/36615
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=419216&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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