3 Dimensional transmission line matrix (3D TLM) modeling and analysis of through silicon via (TSV) coupling in 3 dimensional integrated circuit (3D IC)

Abstract

3D IC is an IC which is stacked in z-direction. To achieve this stacked system, we need some interconnection method between up and down chips. Wire bonding is the conventional methods, but new technology using Through Silicon Via (TSV) have emerged. TSV has short interconnection length, no limitation of location, and can make small size, so TSV is replacing the role of wire-bonding. However TSV also has some disadvantage like thermal problem, noise coupling problem, and manufacturing issues. In my research, I have focused on the noise coupling issues of TSV. TSV is constructed of conductor via surrounded by insulation layer. Insulation layer is for isolation between silicon substrate and conductor via, but this insulation layer is very thin, have high capacitance. So, for high frequency signal, this insulation layer can``t do its original role, isolation. So this high frequency signal can easily be coupled to active circuit which is located near TSV. And degrade circuit performance. In this paper, I have modeled the coupling path between active circuit and TSV, and analyzed the coupling mechanism of this coupling path, also verified the proposed model by measurement. Then, as an application, proposed and verified noise coupling model was used to PLL for performance degradation simulation