DVFS/DCR-based workload distribution-aware 3D-stacked L2 cache design and operation for minimal overall energy consumption

Abstract

As technologies scales, interconnects have become a major performance bottleneck and source of power consumption. Three dimensional (3D) integration such as through silicon vias(TSVs) is promising technology to solve interconnects issues. In microprocessor architecture, 3D-stacked cache have been researched first to solve faced `Memory Wall` problem. There are many researches on 3D-stacked cache design for performance improvement and power reduction. In real-time embedded system, we could reduce energy consumption using both dynamic voltage and frequency scaling(DVFS) and dynamic cache reconfiguration(DCR). To find operating frequency and cache configuration for minimizing overall energy consumption, we have to consider tradeoff between core energy and cache energy. In this paper, we established energy model for microprocessor which have 3D-stacked cache with consideration about physical implementation using TSVs and 3D-thermal distribution. By using established model, first, we propose combined DVFS/DCR method which find operating frequency of core and 3D-stacked cache configuration for given workload and designed 3D-stacked cache. Second, we propose design guideline for 3D-stacked cache, considering workload distribution of real-time embedded system.