DVFS/DCR-based workload distribution-aware 3D-stacked L2 cache design and operation for minimal overall energy consumption = 에너지 소비를 최소로 하기 위한 3차원 적층 L2 캐쉬의 설계 및 동작 방법

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As technologies scales, interconnects have become a major performance bottleneck and source of power consumption. Three dimensional (3D) integration such as through silicon vias(TSVs) is promising technology to solve interconnects issues. In microprocessor architecture, 3D-stacked cache have been researched first to solve faced `Memory Wall` problem. There are many researches on 3D-stacked cache design for performance improvement and power reduction. In real-time embedded system, we could reduce energy consumption using both dynamic voltage and frequency scaling(DVFS) and dynamic cache reconfiguration(DCR). To find operating frequency and cache configuration for minimizing overall energy consumption, we have to consider tradeoff between core energy and cache energy. In this paper, we established energy model for microprocessor which have 3D-stacked cache with consideration about physical implementation using TSVs and 3D-thermal distribution. By using established model, first, we propose combined DVFS/DCR method which find operating frequency of core and 3D-stacked cache configuration for given workload and designed 3D-stacked cache. Second, we propose design guideline for 3D-stacked cache, considering workload distribution of real-time embedded system.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
419143/325007  / 020083089
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ vi, 27 p. ]

Keywords

DCR; DVFS; 3DIC; cache; energy; 에너지; 동적캐쉬재설정; 동적전압및속도변화; 삼차원회로; 캐쉬

URI
http://hdl.handle.net/10203/36584
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=419143&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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