Modeling and analysis of performance degradation on flash analog-to-digital converter affected by power/ground noise

Abstract

Analog-to-digital converter (ADC) is the most important system since ADC is always needed when analog system and digital system coexist on same area. For this reason, ADC can be affected by noise from analog blocks and digital blocks. Power and Ground noise is one of the noise which affects ADC. Coupled power and ground noise affects code missing and generating of ADC outputs, and degrades ADC performance. Power and ground noise, in order to be coupled to ADC chip, is passed through power distribution network (PDN) where ADC chip is mounted. In this course, power and ground noise is changed with PDN impedance. Thus, modeling and analysis of performance degradation on flash ADC affected by power and ground noise is needed. In this paper, modeling of chip-PCB hierarchical PDN is proposed as the form of noise coupling path. Modeling result is noise transfer function varied with noise frequency. The amount of noise coupled to ADC chip is estimated by this transfer function. Also, power and ground noise effects on designed flash ADC are analyzed. Comparators in designed ADC are mainly affected by coupled noise, so operation of a comparator with coupled noise is analyzed. Combined result of noise transfer function and power and ground noise effects on ADC circuit means that PDN impedance model is also contained on ADC performance degradation. This combined result is verified with an experimental result. When PDN is changed with decoupling capacitors mounted on PCB, ADC performance is also changed.