Low power dynamic termination scheme using NMOS diode clampingNMOS 다이오드 클램핑을 이용한 저전력 동적 종단화

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An NMOS Diode Clamped Termination (NDCT) with NMOS threshold voltage (Vth) of around 0 Volt is proposed as a dynamic termination for high speed / low power chip-to-chip interconnection scheme, where both clamping diodes are composed of diode connected and source-to-body tied NMOSFETs. In NDCT, diode connected NMOS with Vth of around 0 Volt is used to approximate an ideal diode. NDCT is very attractive because it is compatible with current CMOS technology without adding too many process steps. We have designed and fabricated the test chip in order to prove experimentally the performance of NDCT with the design rule of 0.35m and triple well process based on CMOS technology having multi-Vth process. We have also fabricated the two micro-strip transmission lines on PCB with the propagation delay times of 2.0ns and 10ns having the characteristic impedance of 50Ω In measuring, pulses with widths of 5.0ns and 100ns having transition time of 1.2ns are adopted as incident pulse toward transmission line. Both simulation and experimental studies show that, compared with Open Termination (OT), the magnitudes of overshoot and undershoot for nsec range input pulse are constant at less than ~15%, regardless of applied supply voltages (Vcc = 3.3V, 2.5V, 2.0V and 1.8V), with same order of magnitude in power saving. The studies also show very clean signal integrity, regardless of applied supply voltages (Vcc), and lower power dissipation compared with Diode Termination (DT). This good performance of NDCT mainly comes from the small magnitude of reflected wave due to the low Vth of NMOS diode. Lastly, the NDCT is found to be very immune to Electro-Static Discharge (ESD), guaranteeing more than 3000 Volts for Human Body Model (HBM). This is because the static-charge that is introduced to input is effectively discharged by the low-Vth and wide width of NMOSFET. All of these demonstrate the potentiality of NDCT as the high speed interconnection scheme and make the NDCT scheme as a...
Advisors
Lee, Kwy-Roresearcher이귀로researcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1999
Identifier
151016/325007 / 000955195
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1999.2, [ iv, 100 p. ]

Keywords

Low-Vth NMOS transistor; NDCT; Dynamic termination; Transmission line; NDCT; 전송선; 낮은 문턱전압 NMOS 트랜지스터; 동적 종단기

URI
http://hdl.handle.net/10203/36515
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=151016&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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