Design and performance analysis of a general expansion architecture for large-scale ATM switches

Abstract

Future public backbone ATM switches may require 1 Tb/s switching capacity. However, most ATM switches currently developed have a limited switching capacity due to their architectural limitations. Large-scale switches need to have modular, multistage architectures to overcome physical limitations on the circuit compleixty and the number of I/O pins of an LSI chip or a PBA. Utilizing a general modular switch architecture can increase the switching capacity even by using conventional small ATM switches. In this dissertation, we propose a general expansion architecture which can be used in building large-scale switches using any type of ATM switch. The proposed Universal Multistage Interconnection Network (UniMIN) switch is comprised of a buffered distribution network (DN) and a column of output switch modules (OSMs) which can be any type of ATM switch. ATM cells are routed to their destination using a two-level routing strategy. The DN provides each incoming cell with a self-routing path to the destined OSM, which is the switch module containing the destination output port. Further routing to the destined output port is performed by the destination OSM. Use of a channel grouping technique yields excellent delay/throughput performance in the DN, and the virtual FIFO concept is used for implementing the output buffers of the distribution module without internal speed-up. We also propose a "fair virtual FIFO" to provide fairness between input links while preserving cell sequence. The DN is comprised of a single type of distribution module which has the same size as the OSM, regardless of the overall switch size N. This gives good modular scalability in the UniMIN switch. Performance analysis for uniform traffic and hot-spot traffic shows that a negligible delay and cell loss ratio in the DN can be achieved with a small buffer size, and that DN yields robust performance even with hot-spot traffic. In addition, a fairness property of the proposed "fair virtual FIFO" i...