(A) study on VLSI implementation for high-speed/low-power error correction coding applications

Abstract

In this dissertation we present a construction method of BCH and RS encoder/decoder with special emphasis on minimizing power consumption and increasing the throughput per unit time to reduce the energy-delay product. A new long polynomial division algorithm in finite field based on the lookahead of partial-remainder(LAPR), is proposed. Since our algorithm is based on partial-division on orthogonal group basis and lookahead technique exploiting the linearity in finite field arithmetic, it is possible to completely eliminate polynomial multiplications leading to highly increased throughput per unit time. The inherent regularity and feed-forward nature of our algorithm make it possible to be fully pipelined. When pipelined, its throughput is 1 quotient and 1 remainder per clock cycle regardless of the degree of dividend polynomial, which is orders of magnitude faster than the conventional architecture using LFSR(Linear Feedback Shift Register). An area efficient sequential architecture based on LAPR is also presented. Although, the throughput rate of sequential architecture is rather lower than that of the pipelined one, as far as the authors know, it is still higher than that of any division architecture ever reported. Those will be shown to be efficient, regular and easily expandable, hence, naturally suitable for VLSI implementation. We verified the general validity of the division algorithm based on LAPR by mathematical manipulation and simulation. To verify the relative performance of the proposed division architectures over the conventional one using LFSR, we designed three popularly used BCH/RS coding applications 1) (32,28) RS encoder, 2) (63,51) BCH encoder 3) syndrome generator for (63,51) BCH decoder construction in COMPASS ASIC development environment using $0.8 \mu m$ double metal CMOS technology. Experimental verification for three benchmark circuits show that at identical throughput, pipelined architectures based on LAPR consumes about 32, 65, 67 t...