Bypassing omega network for high speed packet switching고속 패킷 스위칭을 위한 통과 오메가 망

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This thesis propose a switching network called as bypassing omega network which is multi-stage interconnection network. This network has several switching stages where each stage consists of $\frac{N}{2}$ switching elements which does 3×3 switching individually. The connection between adjacent stages consists of the perfect shuffle and horizontal connection. The perfect shuffle connection connects the input of one switching element with two switching elements of previous stage; one is at the upper group and the other is at the lower group. The horizontal connection is done from the switching element in a stage to the same position switching element of next stage. The connection pattern between adjacent stages are same throughout the system. The number of such connection at the bypassing omega network with $S_{total}$ stages is $S_{total}-1$. The design basis of the network is the implementation aspect of the switching network into VLSI chips. When someone are going to partition the switching network into modular VLSI chip, the number of required chips and chip kinds become the main decision parameter. The number of chip kinds for the system implementation should not be great and the number of total chip in the system should be small. Even though, the number of integrated gates in a chip rapidly increased as the VLSI technology evolves but the number of pin count in a chip did not increase as much as that of the gate counts. The proposed bypassing omega network is adequate for the modular partition of the switching network because it requires smaller number of stage and less interconnection wires and less pin counts in the system. The bypassing omega network, also, has very regular connection pattern so that the system modularity is very high. This regular pattern enables high fault tolerance and easy maintenance. The operations of each switching element are simple and straight forward. The operations are routing, bypassing, deflection and discarding. The routin...
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1997
Identifier
114103/325007 / 000865355
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1997.2, [ xiii, 98 p. ]

URI
http://hdl.handle.net/10203/36358
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=114103&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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