1GHz low noise frequency synthesizer design for digital mobile communication using monolithic CMOS technology = 디지탈 이동통신에 적합한 monolithic CMOS 기술을 이용한 1GHz 급 저잡음 주파수 합성기의 설계

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The implementation of a single-chip, low noise CMOS PLL frequency synthesizer for wireless communication applications has been presented. The circuit is composed of three main components, i.e., a Voltage-Controlled Oscillator (VCO), 1 / 7, 8 dual-modulus prescaler and a Phase-Frequency Detector (PFD). The circuit is fully integrated with the exception of the loop filter components in a standard digital 0.8㎛ CMOS process. To be immune to noise, all the circuits in the synthesizer use the differential schemes and the digital parts are designed by the static one. A new high speed low noise VCO with precise signal swing control has been proposed. While the VCO output frequency can be controlled by the current of the each delay cell, each of the maximum and the minimum voltage levels can be controlled precisely by the respective reference voltage. Since this overhead circuit does not increase the output load, we succeed to obtain VCO operating in GHz range. With this method, the output swing levels are controllable independently of the power supply and the ground and thus a level shifter and an amplifier are not needed. Another new high frequency ring oscillator suitable for multi-phase clock generation has been proposed. The ring oscillator consists of inverters with negative delay elements that are derived from the other nodes in the ring oscillator circuit. In this way, it is possible to obtain the cell delay of the ring oscillator which is smaller than the fundamental inverter delay. Simulations show that the resulting operating frequencies can be twice as high as those obtainable in the conventional approaches. A new VCO combined with the new ring oscillator has been also studied. Simulation shows that the 25% higher operating frequency can be obtained compared with the conventional approach. A new D flip-flop with a single clock, differential static scheme for a dual-modulus prescaler has also been proposed. The maximum operating frequency of 1.45GHz ...
Advisors
Lee, Kwy-Roresearcher이귀로researcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1996
Identifier
108815/325007 / 000895360
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1996.8, [ vi, 112 p. ]

Keywords

Mobile communication; Frequency synthesizer; Voltage controlled oscillator; 전압제어발진기; 이동 통신; 주파수 합성기

URI
http://hdl.handle.net/10203/36344
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=108815&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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