Reliability study and effect of NH3 annealing on the electrical characteristics of polysilicon thin film transistors = 다결정 실리콘 박막 트랜지스터의 신뢰성 연구 및 암모니아 열처리가 전기적 특성에 미치는 영향

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 339
  • Download : 0
For obtaining the high performance polycrystalline silicon (poly-Si) thin film transistors (TFT``s), the enhancement of on-state current and the reduction of off-state current is the most important issue to be solved. In this thesis, we have investigated the methods for improving poly-Si TFT``s such as melt-regrowth of amorphous silicon (a-Si) and hydrogenation of poly-Si TFT``s, and surveyed the reliability of poly-Si TFT``s, and suggested the way for suppression of leakage current. We have proposed the new method of obtaining the lower solidification velocity, i.e., large-sized grain, using Xenon flash lamp as light source with pulse width of micro seconds and simulated numerically the system of silicon-silicon dioxide-glass using one-dimensional simulator. We have found that the condition for obtaining the low solidification velocity is peak power of 0.3 MW/cm2, and light pulse width of 12 usec, which can be practically controlled by charge circuit, and then at this condition, the solidification velocity is 0.066 m/sec, which corresponds to the grain size of about 3.5 um. This outcome is the best one of the reported ones, having the possibility of the practical application. We have also investigated the hydrogenation effects on the top-gated and bottom-gated poly-Si TFT``s using the electron cyclotron resonance (ECR) plasma system. In conventional top-gated structure, the effect of hydrogenation is strongly dependent on the channel length. We have proposed the new process for short-time and simple hydrogenation by employing the gate poly-Si with hemispherical grains and designed the preliminary structure having this gate poly-Si. We have investigated the reliability of bottom gated n-channel poly-Si TFT``s under the various bias conditions. For stressing under the linear region, we can find that the main degradation mechanism is the hole injection into the gate oxide. The hole trapping induces the parallel threshold voltage shift to the negative direction, a...
Advisors
Kim, Choong-Ki김충기
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1995
Identifier
101722/325007 / 000855413
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1995.8, [ v, 160 p. ]

Keywords

ammonia annealing; TFT; polysilicon; positive fixed oxide charge reliability; 신뢰성; 양의 고정 산화막 전하; 암모니아 열처리; 박막트랜지스터; 다결정실리콘

URI
http://hdl.handle.net/10203/36292
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=101722&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0