(A) study on the delay modeling for sub-micron CMOS logic and its application to performance optimization

Abstract

This dissertation mainly concerns two areas of the CMOS digital circuit design. They are the transistor level CMOS delay modeling and the circuit level performance optimization with transistor sizing. For the delay estimation, a new delay model is presented in two parts which consider the short channel and the internal parasitic capacitances effects. As the first part, a closed-form of the inverter delay is derived from the modified MOS current equation of SPICE level 3. To derive the delay formulation, we show that only saturation region with short channel effects is suffice. As a results, the model considers many parasitics such as input-to-output coupling capacitance, lowering drain saturation voltage, mobility degradation, carrier velocity limitation, and channel length modulation. Also, the series resistance effect which can be large in LDD process is considered. As the second part, the effect of internal parasitic capacitances is analyzed by two steps. In the first step, the circuit is divided into two parts owing to the effect of parasitic capacitances. In the second step, the delay differences are calculated which are the contributions of parasitic capacitances in Series-Connected MOS Structure (SCMOS) to the propagation delay and they appear as the voltage waveform shift. After all, the proposed delay estimation scheme evaluates SCMOS propagation delay through three steps, which are the calculation of the delay differences, that of the propagation delay of equivalent inverter, and the addition of the two. The experimental results show several important characteristics of SCMOS. The first is the delay differences are almost independent to input slope and load capacitance. The second is merely saturation operation of short channel MOS can estimate the propagation delay accurately. Moreover, the property becomes more severe as channel length becomes shorter. Various experimental results show the proposed method for delay difference calculation can signifi...