(A) study on the low voltage deep submicron nMOSFET design and reliability

Abstract

A new MOSFET structure called Compensated Channel nMOSFET (CCMOSFET) has been proposed as an alternative channel structures to lower threshold voltage for low voltage/low power operation with good control of short channel effects(SCE) in sub-0.1㎛ devices, and Device and/or Circuit reliability characterization and projection also have been provided. Device simulation results show that CCMOSFET has much smaller SCE compared with other alternative structures for power supply voltage less than 1.5 volts. To facilitate MOSFET performance/reliability trade-off, we also propose the E-PLOT method, which is simple and straightforward method to give physical insight into device characterization and design. The salient features of this approach is that it allows us to separate the respective contributions from the saturation voltage and device structure to the substrate current, and more importantly to characterize the time evolution of the substrate current systematically. The effective critical energy for interface state generation during hot-carrier stress has been investigated using the rate equation based on the lucky electron model. The time dependence of interface state generation has been formulated from the measured critical energy. It is found that the major physical mechanism responsible for the saturation behavior of degradation is the enhancement of critical energy. This work provides more accurate and physical reliability projection than the conventional purely empirical power-law model. Moreover, in this proposal, a new approach for simulation of circuit degradation due to hot carrier damage in LDD nMOSFET is presented. Current degradation was modeled by a external source/drain resistance change which is also applicable to bidirectionally stressed devices as well as much more efficient for circuit simulation. This new model can easily be implemented in any circuit simulator.