Critical path verification and optimization of CMOS digital designs = CMOS 디지틀 설계의 임계경로 검증 및 최적화

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This thesis is mainly concerned with two areas in the design verification of CMOS digital circuits. First, critical path verification involves identifying critical paths and estimating propagation delays along these paths. It automatically searches all possible paths without the need for test patterns. This static approach is particularly efficient and useful for large systems because simulations can be prohibitively long if an extremely large number of input stimulus need to be proecssed. Thus, it has been an essential tool in the design of digital integrated circuits. Second, even if the critical paths are known, designer still need an assistance to improve the circuit performance. Therefore, it is important to provide the information to the design of digital circuits by finding the optimum transistor sizes. In this dissertation, we present a new switch-level critical path verifier and optimizer called KCROP which determine the maximum operation speed of a system and provide resizing capability to re-design the chip without requiring many iterations between simulation and verification tools. The signal flow throgh MOS transistors is determined by combining the designer``s tag with a set of direction dervation rules, and the delays are evaluated on a stage-by-stage basis. We also investigate a novel methodology to report multiple paths, to be called a modified depth-first search with predictor because reporting only one critical path to the designer often fails to give user-informative pathe. Compared to the conventional method without predictor, it requires much less CPU time. At the switch level, the transient behavior of a digital CMOS circuit is approximated by that of an RC network for evaluating delays. While the previous switch-level delay models are very efficient, they may not be accurate enough to calcuate the longest paths in a design. This thesis employs a semi-analytic CMOS delay time model which takes into account the configuration ratio, input w...
Advisors
Lee, Kwy-RoresearcherPark, Song-Bairesearcher이귀로researcher박송배researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1991
Identifier
61698/325007 / 000845024
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 1991.2, [ v, 137 p. ]

URI
http://hdl.handle.net/10203/36139
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=61698&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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