(A) mixed-mode simulator for analog/digital circuits using event driven waveform relaxation method

Abstract

For the analysis of VLSI circuits which contain both digital and analog circuits, neither circuit nor logic simulation alone is sufficient. Although logic and timing simulators are generally faster than circuit simulators, they are inadequate for simulation of analog circuits and critical parts of digital circuits, where circuit simulation is required. Therefore, a mixed-mode simulator which combines circuit, timing and logic simulations, is currently one of the most effective tools of timing verification of VLSI circuits which contain both digital and analog circuits. Many mixed-mode simulation programs have been developed and used in practical VLSI circuit designs. In this thesis, we propose a new mixed-mode simulator called KMIX which combines gate level logic simulators, multiple delay and switch level simulators and timing and circuit simulators, all of which utilize a common database. The waveform conversion between analog and digital waveforms is carried out by using a threshold function. For the convergence check of waveforms, the above simulators use an event waveform relaxation method. The algorithms used in the respective simulators follow. The timing and circuit simulators are based on the waveform relaxation method and exploit the signal flow along the feedback loops. Each of the feedback loops is treated as one circuit block and then local iterations are performed to enhance the simulation speed. For the MOSFET model, we propose two non-physical models which follow the piecewise polynomial approach but do not require any interpolation in actual determination of the drain current. In the multiple delay and switch level simulators, we propose a new delay model for the rise/fall delay times. The delay times are calculated for each logic gate from the stored values of polynomial coefficients and from the effective configuration ratio, the effective input waveform slope and the load capacitance. This process does not require any interpolation and hence...