This dissertation describes the design methodology of VLSI system design by using redundant binary (RB) number system. Especially, the methodology for fused-MADD (multiplication and addition) RB floating-point (FP) datapath unit is discussed. In order to acquire the benefit of carry-free addition, the whole FP functions including multiplier, significand adder, normalization block and rounding block are designed to support RB operation.
First, the mathematical algorithm for RB normalization is proposed. Because of the redundancy of RB number system, one normal binary (NB) number can be represented with various RB numbers which has not determined precision length and exponent. However, the proposed zero-addition method limit the length of precision, and the zero-added result has at most two more bits than the NB converted number. With additional operation, the precision of RB number is limited to have one more bit than the converted number, and then the whole RB FP operation is enabled with previously established RB addition rule and RB rounding algorithm. With the pre-normalized RB number by zero-addition, two kinds of RB number formats for floating-point operation are proposed: fixed-precision number format (FPNF) and variable-precision number format (VPNF). FPNF has the compatibility with IEEE 754 standard, and the implemented RB FP unit uses FPNF to support the IEEE standard compatibility.
Then, the `` fused-MADD FP unit with proposed RB datapath algorithm is designed and fabricated. It implements the RB bypass structure to conceal the RB-to-NB conversion overhead. 53b × 54b RB multiplier for double precision format is proposed and implemented. To support the RB bypass structure, the multiplier gets 54b FPNF RB number as its input operand.
Significand adder consists of two adders, one for significand RB addition and the other for the pre-normalization with zero-addition. The proposed structures of RB rounding and normalization contribute to minimize the laten...