TLB and memory architecture for high TLB reach and superpage utilization티엘비 용량과 수퍼페이지 이용을 높이기위한 티엘비 및 메모리 구조

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 932
  • Download : 0
A TLB (Translation Lookaside Buffer) is a cache in a processor to accelerate the translation of a virtual address to a physical address. Since the working set of application programs has been increasing rapidly, TLB reach - the maximum size of the memory mapped by a TLB - is failing to keep pace with it. A TLB is a very expensive resource in a processor and it should operate in a high speed. Therefore, there are strong limitations in increasing the number of TLB entries. Superpage approach was proposed to increase TLB reach without increasing the number of TLB entries. In a superpage TLB, a TLB entry can map a superpage which is several contiguous base pages. There are several strong requirements for using superpages, and they hinder the actual utilization. Two previous schemes, a partial-subblock TLB and the shadow memory were proposed to release the requirements. A partial-subblock TLB releases only a small portion of the requirements and also limits the superpage size. The shadow memory releases most of the requirements but introduces other serious problems. This dissertation explores various schemes for supporting superpages efficiently and increasing actual utilization of superpages. First, this dissertation proposes a hybrid scheme which integrates the shadow memory and a partial-subblock TLB, thereby enjoying the benefits inherited from both sides. The hybrid scheme has as high a superpage utilization as the shadow memory, and avoids most of the problems in the shadow memory by virtue of the partial- subblock TLB. The hybrid scheme inherits most of the hardware cost and overhead from both schemes. However, the evaluation shows that the performance gain overwhelms the cost and overhead. Second, this dissertation introduces a new TLB structure, called VS-TLBs. They are based on subblock TLBs and add the subblock size field. By virtue of the subblock size field, a subblock in VS-TLBs can be multiple pages, while a subblock in the subblo...
Advisors
Park, Dae-Yeonresearcher박대연researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2002
Identifier
174610/325007 / 000975144
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ 75 p. ]

Keywords

VS-TLB; Superpage; VS-hybrid; 티엘비; 수퍼페이지; TLB; Hybrid

URI
http://hdl.handle.net/10203/35978
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174610&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0