(A) DLL-based frequency synthesizer with selective reuse of a delay cell scheme for 2.4 GHz ISM band = 선택적 지연셀 재사용 기법을 사용한 2.4 GHz ISM band DLL 기반의 주파수 합성기

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For the design of communications circuits, the ultimate goal is to implement a single chip transceiver with the minimum number of off-chip components. A high level of integration enables significant cost and size reduction. However, for a cost-effective CMOS process, one of the most challenging parts of transceiver integration is the realization of low phase noise synthesizers with low-Q on-chip components. One approach overcoming the limitation is to use an LC-tank voltage controlled oscillator (VCO) with a Q-enhancing technique for the inductor [1]. Another approach is to use a delay-locked loop (DLL) and a frequency multiplier with an edge combiner [2]. The phase noise is improved because no timing jitter is accumulated from cycle to cycle when DLLs are used. However, the number of delay cells determines the multiplication factor and the multiplication factor is fixed. Consequently, the latter method has limitations whenever a variable or a large multiplication factor is required. This paper presents a DLL-based frequency synthesizer that selectively reuses a delay cell. By switching the number of delay cells that a signal goes through in a proper sequence, the frequency synthesizer can generate multiple frequency output with a small number of delay cells. With only 9 delay cells, the test chip achieves frequency multiplication factors greater than 240. It also provides multiple frequency output by adjusting the multiplication factor similarly to a conventional frequency synthesizer. This work describes a 2.4 GHz frequency synthesizer based on a delay-locked loop (DLL). Because the proposed frequency synthesizer is basically developed from a DLL, it has no jitter accumulation thereby resulting in a low close-in phase noise of -105 dBc/Hz. Although only 9 delay cells are used, the proposed delay cell reusing scheme realizes frequency multiplication factors greater than 240 and provides multiple frequency output with the resolution of phase detector (PD) compa...
Advisors
Kim, Beom-SupresearcherKim, Lee-Supresearcher김범섭researcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2004
Identifier
240731/325007  / 020005006
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2004.8, [ viii, 76 p. ]

Keywords

DELAY-LOCKED LOOPPUT FEEDBACK; TIME-DELAYNBERG MARQUART LEARNING; UBIQUITOUS COMPUTING; PERSONALIZED SERVICE; 주파수 합성; 대역내 위상잡음; 지연동기회로 궤환; 시지연 마코프 모델; 레벤버그 마큇 학습; 유비쿼터스 컴퓨팅; 개인화 서비스; FREQUENCY SYNTHESIS; IN-BAND PHASE NOISE

URI
http://hdl.handle.net/10203/35937
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=240731&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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