Processor and memory interface architecture for HDTV decoding

Abstract

As the high-definition television (HDTV) broadcasting starts, video signal processors must cope with a large amount of video data within a tightly bounded time frame. Hence, performance of the processors and memory bandwidth with external memories become very crucial factors to design HDTV decoding systems. Moreover, the processors are required to a high degree of programmability and fast task-switching features for supporting various standards without hardware redesign and real-time processing. In this thesis, we discuss both the processor and the memory interface architectures for HDTV decoding applications that have characteristics such as a lot of data-level and instruction-level parallelisms and pre-deterministic operation sequences. First, we propose a processor architecture that meets three requirements i.e., high-performance, programmability and fast task-switching. The proposed architecture features a 4-way VLIW execution pipe and special instructions to achieve high-performance and programmability. Owing to a multi-thread scheme, the processor can execute two independent programs simultaneously without incurring any switching overhead. Lastly, conditional execution instructions and condition generation hardware are used to prevent conditional branches from degrading the instruction-level parallelism and the system performance. Experiment results show that the proposed architecture can achieve 5.4$\times$ speedup over a simple scalar architecture and meet the processing requirement for decoding MP@HL video streams regardless of the number of bi-directional macroblocks. Second, we propose a high-performance and low energy consumption memory interface architecture for Synchronous DRAM (SDRAM)-based image processing applications. The proposed architecture includes an array address translation logic that transforms logical array addresses into physical memory addresses so as to minimize the number of overhead cycles needed for row-changes. We present sev...