In this dissertation, we are concerned with the issues on design and performance analyses of a scalable multicast ATM switch system with asymmetric switch elements.
First, we propose a switch module with quasi-shared buffering. The proposed switch adopts a switch architecture with separated buffers shared between input and output ports. For sharing dedicated buffers within the switch module, a simple distributor and fast arbiter are proposed. The proposed distributor delivers incoming cells evenly into several dedicated buffers and the arbiter resolves contentions of the cells destined for the same output port. The size of output group and the size of output port per output group can be changed by simply changing the number of cross-point columns located in the cross-point output switch and the arbiter. The performance is evaluated through both numerical analysis and simulation in terms of throughput, mean delay, cell loss probability, and buffer requirements.
Second, we propose a scalable multicast ATM switch system with asymmetric switch modules. For building the proposed switch system, we propose a routing algorithm, a multicasting table management algorithm, an internal cell format, and an interconnection method of the switch modules. The proposed routing and cell-splitting copy algorithm can reduce the required buffer size for multicasting routing table and the traffic load on the links within the switch fabric. And we explain the necessity of asymmetric switch systems, and show several numerical examples. The performance of the system is evaluated through both numerical analysis and simulation in terms of throughput, mean delay, cell loss probability, and buffer requirements.
Third, we propose a new cell re-sequence mechanism and an implementation method for multipath ATM switches. Since the proposed mechanism uses per-VC logical queues that store only the cells belonging to the same VC, the mechanism can reduce the processing time compared with conven...