New self-aligned offset polysilicon thin film transistors = 자기 정렬 오프셋 구조를 가지는 새로운 다결정 실리콘 박막 트랜지스터

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New self-aligned offset polysilicon thin film transistors (poly-Si TFT``s) have been investigated to reduce the leakage current. Both types of self-aligned offset poly-Si TFT````s have been developed; coplanar one using photoresist reflow, and staggered one using planarization with thick photoresist and etchback. Effects of trap density on the leakage current of poly-Si TFT````s with the offset structure have also been investigated. A simple fabrication method to realize self-aligned offset poly-Si TFT````s has been developed for the coplanar structure. The self-aligned offset structure can be achieved without any additional mask and masking material. The process is based on the photoresist reflow, which can be controlled by varying photoresist thickness and reflow temperature. It is found that the reflow length of photoresist increases in proportion to the photoresist thickness, and increases with increasing reflow temperature at less than 200℃ for the AZ5214A photoresist. Poly-Si TFT````s have been successfully demonstrated with offset lengths of 0.4 ㎛ and 0.6 ㎛, which show apparent reduction of the leakage current. To realize the offset structure in the staggered type, a new self-aligned offset poly-Si TFT has been proposed and successfully fabricated to have a symmetrical offset with controllable offset length. The self-aligned offset is formed by photoresist planarization and etchback without any lithographic step. The offset length can be easily controlled by the thickness of gate material. The fabricated staggered poly-Si TFT````s have shown significantly reduced leakage current and symmetric electrical characteristics. It is noted that with this process, sub-micron channel staggered poly-Si TFT````s can be fabricated without photolithographic limitation. Effects of trap density on the leakage current of poly-Si TFT````s with the offset structure have been investigated. In the solid-phase crystallized (SPC) device with high trap density ($~1×10^{13}/...
Advisors
Han, Chul-Hiresearcher한철희researcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1999
Identifier
156188/325007 / 000955411
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1999.8, [ iv, 120 p. ]

Keywords

Photoresist; TFT; Polysilicon; Self-alinged offset; Staggered; 스태거형; 감광막; 박막트랜지스터; 다결정실리콘; 자기 정렬 오프셋

URI
http://hdl.handle.net/10203/35808
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=156188&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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