The source and drain structures of MOS transistors suitable for high density CMOS IC``s are proposed and their applications to CMOS chips are investigated experimentally and theoretically. The first part of the investigation is concerned with a new self-aligned MOSFET structure with polysilicon source and drain electrodes to increase the IC packing density. The proposed structure is capable of reducing the device size by about 50% over conventional MOSFET. In the second part of this thesis, a PtSi Schottky-Clamped CMOS (SCCMOS) technology which combines p-channel Schottky-clamped MOSFET``s and n-channel conventional MOSFET``s is devised to suppress the latchup problem in CMOS circuits. The SCCMOS structure with 6 ㎛ n+/n-well spacing and 12 ㎛ n-well/p+ spacing shows experimental holding voltages larger than 7 V and holding currents above 10mA. The modeling of the latchup phenomenon in SCCMOS structure using SPICE shows that a higher holding voltage is achieved when 1) the ideality factor of the Schottky diode is closer to unity, 2) the saturation current of Schottky diode is larger and 3) the width of the p+ emitter in the Schottky-clamped pnp transistor is narrower. Finally, another SCCMOS technology which clamps the source junction with $TiSi_2$ Schottky diode while employing conventioal drain junction is proposed. In this structure, the Schottky-clamping effect can be substantially increased due to the lower Schottky barrier height of 0.6 eV in $TiSi_2$/n-Si contact while the drain leakage current problem related to Schottky diode is completely eliminated. The fabricated SCCMOS where n+/n-well and n-well/p+ spacings are 5 ㎛ and 11 ㎛ respectively shows experimental holding voltages above 7 V and holding currents above 10 mA although the ideality factor has been measured to be 1.4 which is rather high.