High-performance MOS analog multiplier and temperature-stabilized SOI voatage reference고성능 MOS 아날로그 곱셈기 및 온도안정화된 SOI 기준전압회로

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High-performance MOS analog multiplier and temperature-stabilized SOI voltage reference are described. First, the multiplier is based on the square-law dependence of the MOS transistor drain current on the gate-to-source voltage in the saturation region. One input is applied to the gate directly while the other input is applied to the source through a source follower buffer stage. The mulitiplier circuit is realized with only 12 MOS transistors and 2 resistors. The circuit has been fabricated using a metal-gate NMOS process which has separate p-wells to eliminate substrate bias effects. The multiplier achieves less than 0.45\% nonlinearity when the input voltage range is 40\% of supply voltages, and a-3dB bandwidth of 30 MHz. The total harmonic distortion (THD) is less than 0.6\%. The second-order effects for this type of multiplier are considered in detail. Since the multiplier consists of the source followers only and the frequency performance is determined only by the resistance and capacitance at an output node, this configuration of multiplier is very suitable for highfrequency applications. Second, the voltage reference is based on the threshold voltage difference between enhancement and depletion SOI NMOS transistors which have the same channel doping concentration but of opposite-type. The voltage reference circuit has been fabricated on a SIMOX wafer using $n^+$-poly gate and LOCOS isolation process. The threshold voltages of enhancement and depletion SOI NMOS transistors show almost the same temperature dependence. Also, the mobilities of enhancement and depletion SOI NMOS transistors have similar temperature dependence when a suitable back-gate bias is applied. The voltage reference achieves a temperature coefficient of 33. 8ppm/$^\circ$C over the temperature range of -50 to 75$^\circ$C. Since the variation of threshold voltage rifference with temperature is primarily small, this circuit becomes more advantageous as he front-gate oxide scales down or...
Advisors
Kim, Choong-Ki김충기
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1992
Identifier
60509/325007 / 000865217
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 1992.8, [ iv, 103 p. ]

URI
http://hdl.handle.net/10203/35690
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=60509&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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