In this dissertation, novel clock distribution network schemes are proposed to achieve extremely low jitter and skew clock delivery even in severe power supply noise environments, especially for digital chips in 3-D stacked chip packages. Power supply noise generated from digital circuit block causes the clock jitter and skew in conventional H-tree clock distribution network. The first proposed scheme is the designated clock generation and distribution chip scheme, which is extended from star-wiring clock distribution. In particular, the clock generation circuits such as delayed locked loop and clock distribution trees are integrated onto a single designated chip in the multi-stack package. Low jitter and low skew clock signaling is achieved by lower substrate noise coupling from a digital simultaneous switching noise source and by lower inductance of the clock distribution network.
Planar cavity resonator clock distribution network is also proposed and verified. It is based on the uniform-phase of standing wave at the quarter-wavelength planar cavity resonator embedded inside the low temperature co-fired ceramic package level interposer. The clock is converted into sinusoidal wave and induces the standing wave to a planar cavity resonator. The standing wave is re-distributed into the chip through input/output circuit and used for digital data input/output flip-flops. Substantial suppression of the timing jitter and skew was successfully demonstrated through a series of design, analysis, fabrication, and measurement processes of test devices and packages and compared with precious clock distribution networks.
The third one is interposer on-chip clock distribution network in through-silicon via based stacked chip package. The number of clock generator circuit blocks can be reduced and hence, power consumption is also reduced. The reduced clock jitter and skew are achieved by increased routability of on-chip CDN and verified with simulation results.