Design and implementation of NAND flash file system and main memory using phase-change random access memory (PRAM)

Abstract

Non-volatile memory devices such as PRAM (Phase-change RAM), FRAM (Ferroelectric RAM) and MRAM (Magnetic RAM) have been developed as next generation memory devices. Among these, PRAM has begun to gain acceptance as an alternative to embedded storage with its notable features such as non-volatility, random access capability, in-place update, low power usage, and long write endurance. In this thesis, we study the use of PRAM for NAND flash memory and main memory system. Several flash file systems have been developed based on the physical characteristics of NAND flash memory. However, previous flash file systems still have performance overhead and scalability problems caused by metadata management in NAND flash memory. Therefore we present a flash file system called PFFS2. PFFS2 stores all metadata into virtual metadata storage which employ Phase-change RAM (PRAM). PRAM is next-generation non-volatile memory and will be good for dealing with word-level read/write of small-size data. Based on the virtual metadata storage, PFFS2 can manage metadata in a virtually fixed location and through byte-level in-place update. Therefore, the performance of PFFS2 is 38% better than YAFFS2 for small-file read/write while matching YAFFS2 performance for large writes. Especially, the virtual metadata storage is very effective to decrease the burden of computational and I/O overhead of garbage collection. In addition, PFFS2 keeps 0.18 second mounting time and 284KB memory usage in spite of increase of NAND flash memory size. We also propose the wear-leveling solution for PRAM in the virtual metadata storage and highly reduce the total write count of NAND flash memory. The life span of PFFS2 is longer than other flash file systems. Also, we consider the OS level support to exploit PRAM in current computer system. First of all, we decide to use PRAM with a small size DRAM to overcome the limitation of PRAM. PRAM and DRAM are mapped into single physical memory address space. Then, th...