(A) study on signaling methods and circuits for a high speed memory interface

Abstract

In memory interfaces, the high-bandwidth interface is required to process a large amount of high-speed data such as 3-D graphics. Generally, differential signaling is used for high-speed interface like optical communication, however, single-ended signaling is still used in memory interfaces because the cost per I/O has to be kept low. As the data rate increases and supply voltage decreases, the problems of single-ended signaling such as simultaneous switching noise (SSN), crosstalk and reference offset become serious and they limit the increase of data rate. To overcome the problems of single-ended signaling and to achieve the low cost per I/O, a staggered single-ended signaling with a two references receiver and a pseudo-differential signaling are proposed. A staggered single-ended signaling is used to suppress crosstalk-induced jitter. Since parallel data do not transition simultaneously, the variation of transition mode between data is not generated. As a result, crosstalk-induced jitter is not induced. However, the far-end crosstalk (FEXT) reduces the voltage margin of receiver input signals. To mitigate the voltage margin reduction of receiver input signals, a two references receiver is proposed. In simulation results, the eye of outputs of the receiver using a CML buffer and one reference signal is closed, however, the eye-opening of the receiver using a two references receiver is 135ps. The pseudo-differential signaling to overcome problems of conventional single-ended signaling is proposed. In conventional single-ended signaling, the reference signal from a transmitter is generally used to reduce the common-mode noise which is induced by simultaneous switching noise (SSN). However, as supply voltage becomes low and data rate increases, the reference signal reduces the voltage and timing margin of receiver inputs. There is a termination resistor in the receiver front end of data channels, however, there is not a termination resistor in a reference ch...