Semicustom design methodology for power gated circuits for low leakage applications낮은 누설 전류를 갖는 응용을 위한 파워 게이팅 회로의 세미커스텀 설계 방법

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dc.contributor.advisorShin, Young-Soo-
dc.contributor.advisor신영수-
dc.contributor.authorKim, Hyung-Ock-
dc.contributor.author김형옥-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2009-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=309327&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35513-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ ix, 88 p. ]-
dc.description.abstractIn the design of VLSI circuits, power has been accepted as one of the primary goals. This is because the increasing power consumption in circuits accompanies the considerable cost of systems, more elaborate temperature controller and larger independent energy sources. The leakage current, which exponentially grows in nano-meter scale technology, exacerbates the power issue in circuit design. Hence, power gating has been widely accepted in industries for its efficacy to reduce leakage current. If a circuit is not required for computation for a long period, current switch in power gating turns off the circuit and the considerable part of leakage current can be eliminated. However, the application of power gating to cell-based semicustom design typically calls for customized cell libraries due to its complicated power network, which incurs substantial engineering effort. In this draft, a semicustom design methodology for power gated circuits that enables the unmodified use of conventional standard-cell elements is proposed. In particular, new power network architecture is proposed; it utilizes conventional $V_{dd}$ rails as virtual $V_{dd}$ rails to connect logic cells to current switch, and provides additional $V_{dd}$ rails of higher metal layer. Hence, the new power network enables the use of conventional standard cells, and also permits flexible placement of power gating specific elements. In addition to the power network, the block-based layout method of the current switch is proposed for small area overhead and flexible sizing. The layout method reduces total area occupied by current switch by optimizing isolation space of body of current switch. The design flow for current switch is studied to reduce design time of current switches while guaranteeing voltage drop budget. When a power gated circuit is turned on for computation activity, large number of glitches appear in a circuit due to state restoration of a circuit. To reduce the wasted ener...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectpower gating-
dc.subjectleakage current-
dc.subjectlow power-
dc.subjectsemicustom-
dc.subject파워 게이팅-
dc.subject누설 전류-
dc.subject저전력-
dc.subject세미커스텀-
dc.subjectpower gating-
dc.subjectleakage current-
dc.subjectlow power-
dc.subjectsemicustom-
dc.subject파워 게이팅-
dc.subject누설 전류-
dc.subject저전력-
dc.subject세미커스텀-
dc.titleSemicustom design methodology for power gated circuits for low leakage applications-
dc.title.alternative낮은 누설 전류를 갖는 응용을 위한 파워 게이팅 회로의 세미커스텀 설계 방법-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN309327/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020045076-
dc.contributor.localauthorShin, Young-Soo-
dc.contributor.localauthor신영수-
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EE-Theses_Ph.D.(박사논문)
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