Design of low jitter DLL/PLL for on-chip and off-chip synchronizations = 칩 내부 및 칩 외부 동기화를 위한 낮은 지터의 DLL/PLL 설계

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Synchronization is an important design consideration in most communication and digital processing systems. In synchronous systems, event-oriented operations necessitate the use of clock information. Digital processing systems achieve internal synchronization with clocking. This thesis refers the internal synchronization as on-chip synchronization. For external synchronization in communication systems, a transmitter and receiver need timing alignment between clock and data. This external synchronization is referred as off-chip synchronization in this thesis. For timing alignment of the clock, synchronous systems need feedback loops such as DLL (Delay-Locked Loop) and PLL (Phase-Locked Loop). The DLL is used to align phase in most applications of on-chip synchronization since its stable system allows easy design compared to the PLL. The PLL is required for frequency synthesis in off-chip synchronization applications. Synchronization performance can be evaluated with a BER (Bit-Error Rate) and maximum operating frequency of the system. It directly depends on signal quality in the time domain. Clock jitter measured in the time domain is an important performance parameter of signal quality. This dissertation presents design techniques for low jitter DLL and PLL in applications for on-chip and off-chip synchronizations. The DLL is used to synchronize local clocks with a global clock in the clock distribution network. The proposed DLL has a jitter reduction technique to suppress jitter in noisy environments. It controls the loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability which tracks input phase error. As a result, it reduces the output jitter of the DLL due to low statistical variance of input phase error and narrow effective loop bandwidth. The DLL is implemented in a 0.13μm CMOS process. Under noisy environments, the output clock of 1GHz has 4.58ps RMS and 29ps peak-to-peak jitter....
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2008
Identifier
303622/325007  / 020045812
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2008. 8., [ viii. 99 p. ]

Keywords

synchronization; jitter; phase noise; DLL; PLL; 동기화; 지터; 위상 잡음; DLL; PLL; synchronization; jitter; phase noise; DLL; PLL; 동기화; 지터; 위상 잡음; DLL; PLL

URI
http://hdl.handle.net/10203/35474
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=303622&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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