(A) three-dimensional stacked-chip star-wiring I/O clock distribution networks for low jitter, skew, and delay applications

Abstract

As the clock frequency of digital systems goes up to multi-gigahertz, it is essential to distribute a clock signal to each destination circuits with minimum timing jitter and skew. Usually, cascaded repeaters are indispensable circuit elements in a conventional on-chip clock distribution network, to overcome heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters generate significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by other digital logic blocks located on the same die. In this paper, we present new three-dimensional (3D) stacked-chip star-wiring interconnection schemes to make a clock distribution network robust for both on-chip and package-level power supply noise coupling. The proposed clock distribution schemes provide an extremely low-jitter and low-skew clock signal by replacing on-chip global interconnections with the cascaded repeaters to lossless star-wiring interconnection on a 3D stacked-chip package. The performance of the proposed clocking schemes are verified by simulation and measurement in respect of clock jitter, skew, and delay. We have successfully demonstrated that the proposed clocking schemes provided a 1 GHz I/O clock delivery with 33~36 ps peak-to-peak jitter and a skew of 5~6 ps, while a conventional I/O clock scheme exhibited a 141 ps peak-to-peak jitter and a 16 ps skew in the same on-chip power supply noise of 120 mV peak-to-peak. The proposed 3D stacked star-wiring I/O clocking schemes can get the merits of low jitter and low skew without any loss of power consumption in comparison to the conventional one. Moreover, the proposed I/O clock schemes have reduced 60% of clock propagation delay compared to the conventional I/O clock scheme.