DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Choi, Yang-Kyu | - |
dc.contributor.advisor | 최양규 | - |
dc.contributor.author | Lee, Hyun-Jin | - |
dc.contributor.author | 이현진 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2007 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=268734&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35428 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2007. 8, [ v, 129 p. ] | - |
dc.description.abstract | In this dissertation, fabrication and characterization of 3-dimensional multi-gate silicon nanowire-FET (SiNAWI-FET) using a sub-5nm all-around gate FinFET for high performance logic device with consideration of current direction effects and terabit non-volatile memory device using an 8nm silicon nanowire non-volatile memory (SiNAWI-NVM) with oxide/nitride/oxide (ONO) and omega-gate structure are studied. The sub-5nm N-channel SiNAWI-FET with 1.4nm HfO2 and 3nm silicon channel shows an on-state current of 367A/m at VG=VD=1.0V with the off-state current of 500nA/m, which is normalized by the channel perimeter. The sub-5nm transistor was verified by using 3-dimensional device simulations. Both N-channel and P-channel SiNAWI-FET show threshold voltage increment with a decrement of silicon channel width by quantum confinement effects. And due to the current direction effects of multi-gate silicon nanowire transistor, N- and P-channel SiNAWI-FET show the highest driving current on (110)/<110> crystal orientation without device rotation, whereas most 3-dimensional N-channel device reports higher driving current on 45o device rotation rather than 0o. The fabricated 8nm SiNAWI-NVM with 7nm spherical silicon nanowire channel and 3.8/6.4/5.1nm ONO-structure shows 1.7V VT-window from 12V/80sec program condition. The acceptable electrical characteristics and the excellent erase efficiency of 8nm non-volatile memory with thick gate dielectric layer of ONO-structure are influence of the extremely narrow spherical silicon nanowire channel and omega-shaped gate structure by the superior gate controllability. And the silicon nanowire transistor reliability on the condition of negative bias temperature instability (NBTI) is studied using P-channel SOI and body-tied FinFETs with various fin width and substrate conditions. The NBTI is one of the concept of device reliability which is became major product level reliability challenges for the sub-6... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Multi-gate Nanowire Transistor Reliability NBTI | - |
dc.subject | 다중게이트 나노와이어 트랜지스터 신뢰도 | - |
dc.title | A study of multi-gate nanowire structure fabrication and reliability on the condition of negative bias temperature instability | - |
dc.title.alternative | 다중 게이트 나노와이어 구조의 제작 및 Negative Bias Temperature Instability 관점에서의 신뢰도 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 268734/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 020035251 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.localauthor | 최양규 | - |
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