Modeling and investigation of noise isolation in hierarchical power distribution network (PDN) for 3D system-in-package (SiP)3차원 시스템-인-패키지를 위한 계층적 전력 분배망의 잡음 분리에 관한 모델링 및 연구

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This dissertation presents and verifies a fast and accurate co-modeling and investigation approach of noise isolation analysis in hierarchical power distribution network (PDN) for low-noise 3D system-in-package (SiP) design. It is based on a hierarchical modeling to combine the distributed circuit models at both on-chip level PDN and off-chip level PDN. In particular, it proposes 3D-TLM (Transmission Line Matrix) modeling for the on-chip PDN with a special consideration on the electrical properties of on-chip guard-ring design, on-chip decoupling capacitor design and placement in the on-chip active region. Introducing to the balanced TLM model for the off-chip PDN, the hierarchical model includes all on- and off-chip parasitic circuit elements. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of $Z_{21}$ PDN impedance measurements with a frequency range from 1MHz to 10GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package-PCB hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the on-chip level PDN and the off-chip level PDN. To demonstrate that the proposed model can be applied to the 3D SiP, the 3D-TLM model for TSV (Through-Silicon-Via) has been introduced and connected with the 3D-TLM for the vertically stacked chip. The impact of chip-stacking method in the 3D SiP including TSV structure is investigated by using simulation environment with 3D-TLM modeling. Furthermore, we can demonstrate the noise isolation methodologies at each hierarchical chip-package-PCB PDN. The target transfer impedance specification for minimum phase noise of VCO circuit related to noise coupling from the adjacent digital block has been calculated. To achieve the target transfer impedance specification, the contribution of each noise isolation method has been investigated depending on the target operation frequencies b...
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2009
Identifier
327783/325007  / 020055071
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2009.8, [ xvii, 127 p. ]

Keywords

high frequency modeling; noise isolation; hierarchical power distribution network; system-in-package; 고주파 모델링; 잡음 분리; 계층적 전력 분배망; 시스템-인-패키지; high frequency modeling; noise isolation; hierarchical power distribution network; system-in-package; 고주파 모델링; 잡음 분리; 계층적 전력 분배망; 시스템-인-패키지

URI
http://hdl.handle.net/10203/35373
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=327783&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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