Optimization of wireless receiver and application to dual-band GPS receiver

Abstract

This thesis presents the design and implementation of a low-power, low-cost L1/L2 dual-band global positioning system (GPS) receiver. To build a low-power and low-cost wireless receiver, first, fundamental limits of power consumption of a receiver or a building block are theoretically derived and then several design strategies are presented. Following these strategies, at the system level, all the requirements of individual circuits are properly defined, derived and specified to achieve the given system requirements. At the architectural level, a novel dual-conversion with final low-IF architecture which can be applicable to both L1 and L2 band application with an identical hardware, is proposed. Moreover, the proposed receiver architecture allows the simplest possible PLL architecture that also helps to reduce receiver power consumption. At circuit level, a new circuit topology that performs all the required IF signal processing including filtering, variable-gain amplification, image rejection and anti-alias filtering, is proposed in order to reduce power consumption of the IF strip significantly. The prototype receiver is composed of a RF pre-amplifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-㎛ CMOS technology, the receiver exhibits maximum gain of 95 dB, and noise figure of 8.5 dB, 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image-rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying $2.6-mm^2$ die area including the ESD I/O pads