(A) geometry engine architecture with survived vertex decision algorithm = 살아남는 정점만을 처리하는 방법을 이용한 기하연산 가속기의 구조

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Hardware acceleration technology for 3D graphics becomes ubiquitous from the traditional high-end systems to the portable embedded platforms, as hardware fabrication technology improves. Today``s fastest commodity graphics accelerators are still required to produce real-world complex scenes at real-time rates. Furthermore, future graphics hardware must increase not only its geometry and fill rates but also its flexibility. The demand for more detailed lighting and shading is one of the driving forces behind the desire for more flexibility in 3D graphics. The current graphics hardware is going on ceaselessly rendering more polygons and adopting advanced graphics algorithms for photo-realistic rendering. Removing of the redundant factors in each functional stage of the rendering pipeline directly enhances the processing ability of a graphics accelerator. In the rendering of polygonal models, we have traditionally attempted to quickly remove portions of the model that are invisible with respect to a particular viewpoint in order to reduce the required workloads of the following pipeline stages. One of such approaches is backface culling, which discards the invisible parts of the model at the triangle-level. Generally half of an object is backfacing. In a traditional pipeline, however, backface culling is an efficient technique for reducing the burden of the fragment engines, not for the vertex engines, because it is performed before rasterizing, after vertex transformation. In this thesis, we enumerate and analyze the reasons why modern graphics accelerators do not use this transparent benefit, and propose the hardware-friendly solution. We have performed backface culling earlier than transform and lighting (TnL) to solve the pipeline redundancy, and named that as early backface culling. This approach requires determining which vertices are visible in the input polygonal meshes. To do this, we proposed SVD (survived vertex decision) algorithm and proved the perfor...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2005
Identifier
245085/325007  / 020005343
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2005.2, [ xi, 107 p. ]

Keywords

Processor; Graphics Hardware; Geometry Processing; 기하연산; 프로세서; 그래픽스 하드웨어

URI
http://hdl.handle.net/10203/35298
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=245085&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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