Design and implementation of a programmable QAM VDSL transceiver

Abstract

This thesis describes the design of a complete VDSL transceiver, including ADC, DAC, micro-controller interface, clock generator as well as TC/PMD layer. The ADC has 11-b resolution, 70-MS/s sampling rate, and a differential pipeline structure. The measured SFDR is 67.7-dB at 60-MS/s sampling rate and 20-MHz input. The DAC has 12-b resolution and the maximum sample rate of 100-MS/s based on current-steering architecture. The measured SFDR is 64-dB at 75-MS/s sampling rate and 7.5-MHz sine data. The IIR notch filters are integrated to reduce the interference within amateur radio band and the dual loop AGC is proposed to adjust the gain of a VGA avoiding saturation at an ADC output. Using multiplierless filters, resource-sharing DFE, register files, and independent clock control, the power consumption is reduced to as low as 300-mW at 26-Mbps symmetric transmission, which is one third of the previous approaches. The $I^{2}C$ and SPI interfaces are adopted as the micro-controller interface to set the chip up, to change data rates, and to read the internal data and status. This IC can support up to 13-Mbps data rate over 9000-ft channel with $BER=10^{-13}$. This QAM transceiver for VDSL applications is fabricated in a 0.18-μm 1P6M CMOS process and the die area is 5-mm × 5-mm.