Turbo codes are the most remarkable invention in error correction code and has been proven to show the performance close to Shannon limit. Many of applications move to turbo codes for high performance. however the computational complexity has been the burden to their wide extension. With the improvement of VLSI technology and research on the reduction of computational complexity, turbo codes become close to the users.
Nowadays, the researches on the computational complexity and throughput are usually main topic in many applications using general purpose processor. However, high-throughput and portable application, such as communication with multimedia data and high speed computer access, demand more than the capability of general processor, there should be a study on the VLSI architecture in the aspect of throughput and hardware complexity. This trend is also applicable to turbo decoder design.
First of all, in this dissertation, backward calculation of forward state metric (FSM) is studied. In VLSI implementation of MAP based algorithm, path metric update requires many amount of memory and their read/write operation becomes the most dominant burden in the aspect of power and area. We propose the efficient SISO architecture by reducing the memory and their read/write operation in Log-MAP and MAX-Log-MAP decoder. 20% of power saving can be obtained by our architecture.
The main portion of this dissertation is on the construction method of parallel turbo decoder in the aspect of high-throughput. Multi-SISO architecture is revisited and the inherent data conflict problem is solved using dividable interleaving method. Proposing dividable interleaving method not only solves the I/O conflict perfectly in extrinsic memory update but also reduces the required memory for interleaver. This interleaver shows the same BER performance comparing with conventional method. To show the superiority of our architecture in the aspect of high-throughput, we designed two MAP b...