(A) design of CMOS RF transceiver for 5-GHz band wireless LAN

Abstract

This thesis describes a design of CMOS RF transceiver for 5-GHz band wireless LAN. The IEEE802.11a specification is considered as the framework. The fundamentals of RF transceiver and wireless LAN are presented, which is followed by a new quadrature signal generator that employs a polyphase filter controlled by a DLL loops. The DLL loops reduce the phase error between the quadrature signals. Next, a frequency synthesizer that operates at 5-GHz band is presented. To implement 5-GHz operating frequency divider, both analog type differential divider and true single phase clocking type divider are used. In the direct conversion receive path, a DC offset problem may occur. In order to reduce the offset, a DC offset canceller is introduced. The proposed DC offset canceller eliminates the differential mode DC offset, which can reduce the mismatch problem. Finally, a new power amplifier driver that is power controllable is presented. In order to control the output power in dB scale, a linear-log converter is introduced. A bias voltage generator is also designed and is independent of process, voltage, and temperature variations. The transceiver is implemented in a 0.18-um CMOS technology. Measurement shows that the proposed I/Q generation technique achieves phase mismatch less than 2 degrees. The gain and IIP3 of the receiver is 15 dB and 0dBm respectively. The maximum output power of the transmitter is +0.83 dBm without external power amplifier and the output P1dB of the transmitter is -2.63 dBm.