(An) integrated algorithm for memory allocation and mapping in high-level synthesis = 상위단계 합성에서의 메모리 할당과 배정을 위한 통합적 알고리즘

With the increasing design complexity and performance requirement, data arrays in behavioral specification are usually mapped to fast on-chip memories in behavioral synthesis. In this paper, we over-come two limitations of the previous works on the problem of memory-allocation and array-mapping to memories. Specifically, our key features are (1) a tight link to the scheduling effect, which was totally or partially ignored by the existing memory synthesis systems, and supporting (2) nonuniform access speeds among the ports of memories, which greatly diversify the possible (practical) memory configurations. To support this, we propose an efficient approach which solves features (1) and (2) in an integrated fashion to explore memory configurations more fully and effectively. Experimental data on a set of benchmark filter designs are provided to show the effectiveness of the proposed exploration strategy in finding globally best memory configurations.
Advisors
Kim, Tae-Whanresearcher김태환researcher
Publisher
한국과학기술원
Issue Date
2002
Identifier
174121/325007 / 020003241
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학전공, 2002.2, [ [ii], 31 p. ]

Keywords

memory allocation; high-level synthesis; memory mapping; 메모리 배정; 메모리 할당; 상위단계 합성

URI
http://hdl.handle.net/10203/34468
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174121&flag=t
Appears in Collection
CS-Theses_Master(석사논문)
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