New hardware-based clock synchronisation for the Byzantine fault

A new approach for fault-tolerant clock synchronisation which uses digital clocks instead of the conventional PLLs(phase-locked loops) is presented. In this circuit the delay time of the clock system is much reduced and the exact maximum clock skew is obtained to guarantee the tightness of the synchronisation.
Publisher
Institution of Engineering and Technology
Issue Date
1992-10
Keywords

Computer metatheory; Hardware fault-tolerant clock synchronisation; Byzantine fault; Interactive convergence algorithm

Citation

Electronics Letters, Vol. 28, No. 21, P.2018 - 2019

ISSN
0013-5194
URI
http://hdl.handle.net/10203/3375
Link
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=170897
Appears in Collection
CS-Journal Papers(저널논문)
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