Generation of cell descriptions from regitster transfer language description for datapath = VLSI 자료 통로의 RTL 표현에서 세포 표현의 생성

This thesis describes a system, as a part of a silicon compiler, which generates cell descriptions from the register transfer language description of a datapath on a VLSI design. To reduce the complexity of design effort, we devise an algorithm which partitions components of a datapath into manageable subgroups. In order to reduce the area occupied by the wires, we emphasize regularity of interconnection of cells. In this system, the interconnections are defined as a part of cell description and adjacent cells are connected by abutment rather than routing. Furthermore, no huge cell library is needed because a description of a cell can always be generated from the cell description in terms of rectangles and polygons. Cell descriptions obtained by this system can be used to generate the physical layout. This system is implemented in about 2000 lines of "C" code and runs on a VAX-11/780 computer under the UNIX(4.2 BSD) operating system.
Advisors
Chung, Won-Lyangresearcher정원량researcher
Publisher
한국과학기술원
Issue Date
1986
Identifier
65182/325007 / 000841312
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학과, 1986.2, [ [ii], 27 p. ]

URI
http://hdl.handle.net/10203/33712
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=65182&flag=t
Appears in Collection
CS-Theses_Master(석사논문)
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