Image processing is a rapidly evolving field with growing applications such as remote sensing, image transmission, medical processing, etc. Most of the image processing applications must handle huge amount of image data in restricted time. Also, it must process lots of elementary operations, where their required data access patterns are quite different. For efficient processing of these applications, the memory system must provide parallel conflict-free accesses for all the required data slices.
This parallel memory system has been given much attention from the early stages of research in parallel processing for numerical applications. While most of the operations for general numerical applications require only disjoint array slices, most image processing operations require arbitrarily placed ones. In the previous storage schemes, only linear skewing schemes meet the requirements. However, these schemes require complex Euclidean Division by a prime number. Nonlinear skewing schemes such as XOR-schemes have advantages in the address generation, but they can support only disjoint array slices.
In this thesis, we propose two parallel memory architectures; one is designed for the general low-level image processing applications and the other is optimally designed for dedicated image processing systems.
We propose a new storage scheme which extends conventional XOR-schemes to provide conflict-free access for arbitrarily placed array slices using the twice number of memory modules than required. We design an efficient addressing hardware for the scheme, which is composed of simple XOR-gates, comparators, and half-adders, etc. We also design a data alignment network extending two N×N Omega networks with two simple 1-stage networks. We also extend proposed memory system for three-dimensional image processing applications. Compared to previous systems using linear skewing, proposed system has better performance in processing time without lots of additional hardware ci...