Path metric memory management for minimising interconnections in Viterbi decoders

To simplify the interconnection between processing elements and path metric memory banks in Viterbi decoders, a new path metric update scheme is proposed based on two techniques, named swapped state grouping and swapped computing. The proposed scheme leads to a simple interconnection consisting of 2 x 2 switches.
Publisher
IEE-INST ELEC ENG
Issue Date
2001-07
Language
ENG
Citation

ELECTRONICS LETTERS, v.37, no.14, pp.925 - 926

ISSN
0013-5194
URI
http://hdl.handle.net/10203/3124
Appears in Collection
EE-Journal Papers(저널논문)
  • Hit : 760
  • Download : 0
  • Cited 0 times in thomson ci
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡClick to seewebofscience_button
⊙ Cited 9 items in WoSClick to see citing articles inrecords_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0