Prediction of Highly Imbalanced Semiconductor Chip-Level Defects in Module Tests Using Multimodal Fusion and Logit Adjustment

Abstract

The memory module is a semiconductor product fabricated by mounting several memory chips on a printed circuit board. In the module test, which is the final step in the memory module manufacturing process, the memory module is tested if it properly functions in the end-user system environment. Then, the chips in the memory module are individually checked for defects to guarantee that the quality matches consumers' expectations. In this study, we propose a framework to predict which chips are defective in module tests using wafer and package test data. However, several challenges must be overcome. First, two different data modalities (i.e., tabular and image data) exist, which influence defect prediction differently for different chips. Second, the module test results are highly imbalanced, with a very low defect rate. To address these challenges, we use a multimodal fusion model that integrates the two different modalities by dynamically evaluating the informativeness of each modality. In addition, we adopt a technique to modify the loss function to be Fisher consistent to minimize the balanced error rate. We demonstrate that the proposed framework can effectively predict chip-level defects in module tests using a real dataset collected from a global semiconductor manufacturing company.