Jitter compensation methods for phase rotator based multi-channel transceiver IC

Abstract

This paper presents methods for lowering deterministic jitter of phase rotator based multi-channel clock and data recovery (CDR) system. In the multi-channel transceiver, each lane is equipped with a phase rotator (PR) to tracking phase/frequency offset among the clock and input data which has lower power consumption and area efficiency than VCO based multi-channel architecture. However, due to structural limitation, the phase rotator is non-linear when rotating, and also current glitch and discrete phase change occurs as the switch is on and off. To minimize the dynamic current glitches from the switch operation, the 10-bit phase rotator without MSB switch is designed, and the non-linearity of the phase rotator was compensated by the digital mapping function. In addition, using the continuous phase delay from analog phase interpolator, discrete phase change of phase rotator is compensated. With proposed compensation methods, the jitter of the recovered clock from 28Gb/s data with 0 to 1000 ppm frequency offset can be compensated to be less than 180 fs RMS at 7GHz quad-rate clock.