Deep neural network (DNN)-based dicing quality estimation method for stealth dicing before grinding (SDBG) process

Abstract

In this paper, we propose a method for estimating wafer dicing quality in a stealth dicing process based on a deep neural network model. Existing methods of verifying process quality based on experiments and measurements consume enormous amounts of time and material resources, but in this study, a deep neural network-based regression model was applied to estimate process quality as a method to eliminate this. With a trained model, the dicing quality corresponding to the process parameter combination of the stealth dicing can be fast and accurately estimated without performing process experiments. Data for model training was generated through process experiments, and errors were minimized by using non-patterned silicon prime wafers for process experiments. The estimation performance was verified by comparing the estimation results of the trained optimal model with the actual process experiment results, and a significant level of time reduction effect and estimation accuracy were confirmed. Finally, the proposed method was applied to a full processed DRAM wafer where all manufacturing processes were completed, and the estimation performance was verified to verify its validity.