Low-temperature fabrication of Ge-On-Insulator substrate with various channel orientation and its analysis for monolithic 3D integration모놀리식 3D 집적을 위한 다양한 기판 방향 별 Ge-On-Insulator 저온 공정 및 분석

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Scaling device size to reduce power consumption reaches the limit due to physical limitations, so research has been conducted to minimize wiring length. In particular, the conversion from the two-dimensional planar arrangement of the device to three-dimensional integration (M3D) could drastically reduce the wire length. However, in the M3D process, the upper Si channel may degrade the device performance due to a high-temperature process, and thus Ge has emerged as an alternative material. Ge is an optimal material for M3D processes because it has good mobility and can be processed even at low temperatures. However, Ge stacking technology for use as an upper device is being developed, but there are clear limitations. Among stacking technologies, the Ge condensation method and the Smart-cut method have excellent crystallinity, but the process temperature is somewhat high. In addition, the HELLO method has disadvantages in that it is difficult to control the doping concentration. In this study, wafer bonding and selective etching were implemented to improve the existing Ge stacking method, a Germanium-on-insulator (Ge-OI) with good crystallinity. To confirm the crystallinity of the manufactured Ge-OI, XRD and RAMAN analyses were conducted, and the surface roughness was measured through AFM to transfer the Ge channel while maintaining excellent Ge crystallinity. The Ge-OI n-MOSFET thus was implemented to measure mobility and subthreshold swing. Before this, the interfacial trap density was reduced by performing plasma pretreatment (PPO) for good mobility, and the interfacial trap density was extracted through the conductance method. The plasma pretreatment is confirmed with a D$_{it}$ of 10$^{11}$ eV$^{-1}$cm$^{-2}$. Accordingly, the fabricated Ge-OI n-MOSFET had the mobility of 528 cm2/V•s and a subthreshold swing of 130 mV/dec. This made it possible to secure Ge-OI capable of controlling the low-temperature process and doping concentration.
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2022
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2022.8,[iv, 24 p. :]

Keywords

M3D▼aGe-OI▼awafer bonding▼ainterfacial trap density▼aMOSFET; M3D▼aGe-OI▼a웨이퍼 본딩▼a계면 트랩 밀도▼aMOSFET

URI
http://hdl.handle.net/10203/309830
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1008362&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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