280.2/309.2 GHz, 18.2/9.3 dB Gain, 1.48/1.4 dB Gain-per-mW, 3-Stage Amplifiers in 65nm CMOS Adopting Double-embedded-Gmax-core

Abstract

This paper reports a sub-THz high-gain amplifier design technique which is more flexible and suitable for performance optimization based on a double-embedded-Gmax-core. The double-embedded-Gmax-cort is implemented by adopting an additional linear, lossless, and reciprocal (LLR) network that satisfies the Gmax-condition (Y21/Y12=-Gmax) on to an N-stage pseudo-Gmax-cores where each stage satisfies the stability factor ki= and phase delay of 2m π/N. Implemented in a 65nm CMOS, the three-stage 280.2 and 309.2 GHz amplifiers achieve power gains of 18.2 and 9.3 dB and gain-per-mW of 1.48 and 1.4 dB/mW, respectively.