Mesochronous bus for reducing peak I/O power dissipation

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A mesochronous bus to reduce the peak I/O power dissipation is proposed. In the proposed bus, subsets of bus lines have nonoverlapping bus transitions in every clock cycle. Experimental results with 0.18 mum libraries show that it outperforms other systems for a wide range of bus frequencies. The reduction rate for a typical 32 bit, 33MHz bus is 90.6%, which is an 81.3% improvement over the previous work.
Publisher
IEE-INST ELEC ENG
Issue Date
2001-03
Language
ENG
Article Type
Article
Keywords

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Citation

ELECTRONICS LETTERS, v.37, no.5, pp.278 - 279

ISSN
0013-5194
URI
http://hdl.handle.net/10203/2971
Appears in Collection
EE-Journal Papers(저널논문)

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