(A) Low-power low-phase-noise frequency synthesizer for mmWave high data-rate wireless communication

Abstract

This study describes the low-power low-phase-noise VCO and frequency synthesizer for mmWave high data-rate wireless communications. The wireless communication in the 60 GHz frequency band allows the multi-gigabit data transmission with 9 GHz wide bandwidth. Moreover, the high speed wireless communication can be implemented through high order modulation. In mmWave wireless communication, the phase noise and jitter of local oscillator are key performance that determines the modulation. The low-power and low-phase-noise VCO and frequency synthesizer for 16-QAM modulation in 60 GHz frequency band are designed and fabricated in 65 nm CMOS process. In 20 GHz frequency synthesizer, the $g_m$-boosting technique with center-tap inductor and third harmonic boosting technique with $gm_3$-boosting circuit are proposed in VCO design. The low phase noise performance of the 20 GHz VCO is obtained by negative conductance boosting and rectangular shaping of the output voltage. The phase noise of the 20 GHz VCO and PLL are -104.11 dBc/Hz and -102.05 dBc/Hz at 1 MHz offset frequency and power consumption are 14 mW and 18 mW, respectively. In 10 GHz frequency synthesizer, the transformer and stacked transistor based gm-boosting technique is adopted in VCO design. The low power consumption and low phase noise performance of the 10 GHz VCO are obtained by negative conductance boosting and voltage gain enhancement between gate and drain. The gm-boosting factor of the proposed VCO is 2.265 and the phase noise enhancement owing to gm-boosting technique is 8.4 dB. The 10 GHz VCO and PLL are integrated in 65 nm CMOS technology. The chip size of the VCO and PLL are $0.66 mm^2$ and $1.54 mm^2$, respectively, including pads. The phase noise of the 10 GHz VCO is -115.4 dBc/Hz at 1 MHz offset frequency and maximum RMS jitter of the 10 GHz PLL is 186.5 fs. The power consumption of 10 GHz VCO core and 10 GHz PLL core are 2.7 mW and 7 mW, respectively. The figure-of-merits of VCO with tuning range and PLL with reference clock frequency are -194.1 dBc/Hz and -250.0 dB, respectively. The 20/40 GHz dual-band frequency synthesizer is designed to generate the 20 GHz and 40 GHz with low phase noise 10 GHz frequency synthesizer. The proposed dual-band frequency synthesizer is implemented in 65 nm CMOS. The chip size of the 20/40 GHz dual-band frequency synthesizer is $1.87 mm^2$, including pads. The measured average RMS jitter of the 20 GHz signal and 40 GHz signal are 169.4 fs and 174.1 fs, respectively. The measured maximum reference spur of the 20 GHz signal and 40 GHz signal are -44.8 dBc and -44.3 dBc, respectively. Additionally, the low-phase-noise 60 GHz injection locked VCO is implemented in 28 nm CMOS. The simulated phase noise, tuning range, and power consumption of the 60 GHz VCO in 28 nm CMOS are -97.75 dBc/Hz, 58.02 GHz ~ 70.02 GHz, and 18.8 mW, respectively. In this dissertation, the 10 GHz frequency synthesizer, 20 GHz frequency synthesizer are designed with low power consumption, low phase noise, and low jitter. Based on 10 GHz frequency synthesizer, the 20/40 GHz dual-band frequency synthesizer for 16-QAM heterodyne transceiver is realized with 14.5 mW power consumption. The proposed frequency synthesizers are suitable for power-efficient wireless communication with high-order modulation.