Signal and power integrity design, modeling, and analysis of a silicon interposer with high bandwidth memory (HBM) for next generation artificial intelligence server

Abstract

Recently, the demands on high-bandwidth and high-density memory systems have rapidly increased to successfully support the super-computing systems used for big data management, artificial intelligence (AI), virtual reality (VR), and so forth. In particular for AI servers, there has been great effort to realize graphic modules with terabyte per second (TB/s) memory bandwidth and dozens of gigabytes (GB) memory density. Fortunately, a 3-D stacked high bandwidth memory (HBM) based on through silicon via (TSV) technology with 1024 data input/outputs (I/Os) has been developed. Inevitably, it is essential to design and analyze of an ultra-fine pitch silicon interposer for HBM interface due to its significant number of I/Os.

Signal and power integrity (SI/PI) design, modeling, and analysis for a silicon interposer must be conducted, because the electrical performance of a system is dominantly affected by a silicon interposer. In this thesis, the multi-coupled channels for HBM interface and differential channels with TSVs for high-speed serial links are discussed. For SI design of the memory interfaces for HBM, the channels designed in a silicon interposer are successfully analyzed and the channel characteristics is verified by the proposed models and an electromagnetic (EM) solver and circuit simulation. In addition, SI of next generation HBM interface with higher data rate data rate is discussed to propose the directions for next generation artificial intelligence servers. The channel including TSVs for differential high-speed serial links are also proposed for SI and the models are also analyzed and verified by EM solver and circuit simulation.

In terms of PI design, power distribution network (PDN) impedance design and analysis are the most important. Therefore, perforated planes with hundreds of TSVs for PDN of a silicon interposer are designed. But it is almost impossible to characterize PDN impedance and verify the proposed PDN structures from EM solver due to the limitation of computing time and resources. To solve the problems, the modeling methodology of PDN impedance is proposed. The proposed PDN models for the proposed perforated power and ground planes with hundreds of TSVs are also successfully analyzed and verified by an EM solver. It is expected that the proposed PDN modeling methodology can be applied to evaluate PI of an entire system for HBM applications.