An in-depth performance analysis of many-integrated core for communication efficient heterogeneous computing

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Many-integrated core (MIC) architecture combines dozens of reduced x86 cores onto a single chip to offer high degrees of parallelism. The parallel user applications executed across many cores that exist in one or more MICs require a series of work related to data sharing and synchronization with the host. In this work, we build a real CPU+MIC heterogeneous cluster and analyze its performance behaviors by examining different communication methods such as message passing method and remote direct memory accesses. Our evaluation results and in-depth studies reveal that (i) aggregating small messages can improve network bandwidth without violating latency restrictions, (ii) while MICs can execute hundreds of hardware cores, the highest network throughput is achieved when only 4 ~ 6 point-to-point connections are established for data communication, (iii) data communication over multiple point-to-point connections between host and MICs introduce severe load unbalancing, which require to be optimized for future heterogeneous computing.
Publisher
Springer Verlag
Issue Date
2017-10-20
Language
English
Citation

14th IFIP WG 10.3 International Conference on Network and Parallel Computing, NPC 2017, pp.155 - 159

DOI
10.1007/978-3-319-68210-5_19
URI
http://hdl.handle.net/10203/269603
Appears in Collection
EE-Conference Papers(학술회의논문)
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