A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices

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dc.contributor.authorLee, Juhyoungko
dc.contributor.authorShin, Dongjooko
dc.contributor.authorLee, Jinsuko
dc.contributor.authorLee, Jinmookko
dc.contributor.authorKang, Sanghoonko
dc.contributor.authorYoo, Hoi-Junko
dc.date.accessioned2019-11-29T06:24:47Z-
dc.date.available2019-11-29T06:24:47Z-
dc.date.created2019-11-27-
dc.date.issued2019-06-
dc.identifier.citation33rd Symposium on VLSI Circuits, VLSI Circuits 2019, pp.C302 - C303-
dc.identifier.urihttp://hdl.handle.net/10203/268711-
dc.description.abstractA high-throughput CNN super resolution (SR) processor is proposed for memory efficient SR processing. It has three key features: 1) selective caching based layer fusion to minimize external memory access (EMA), 2) memory compaction scheme for smaller on-chip memory footprint, and 3) cyclic ring core architecture to increase the throughput with improved core utilization. As a result, the implemented processor achieves 60 frames-per-second throughput in generating full HD images.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleA Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpageC302-
dc.citation.endingpageC303-
dc.citation.publicationname33rd Symposium on VLSI Circuits, VLSI Circuits 2019-
dc.identifier.conferencecountryJA-
dc.identifier.conferencelocationKyoto-
dc.identifier.doi10.23919/VLSIC.2019.8778104-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorLee, Juhyoung-
dc.contributor.nonIdAuthorShin, Dongjoo-
dc.contributor.nonIdAuthorLee, Jinsu-
dc.contributor.nonIdAuthorLee, Jinmook-
dc.contributor.nonIdAuthorKang, Sanghoon-
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EE-Conference Papers(학술회의논문)
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